1. Field of the Invention
The present invention relates generally to test signal generators for semiconductor integrated circuit memories and a testing method thereof. More particularly, the present invention relates to test signal generators for semiconductor integrated circuit memories such as dynamic RAMs self-containing line mode test circuits for reducing time for testing memory cells in large capacity memories and a testing method thereof.
2. Description of the Background Art
FIG. 13 is a block diagram showing an entire structure of a conventional dynamic RAM. Referring to FIG. 13, an address signal Ai is applied to an address buffer 31. The address buffer 31 stores the address signal Ai, applies a row address signal to row decoders 36a and 36b, applies a column address signal to a column decoder 40 and applies a part of the row address signal to a timing generator 32. The row decoder 36a designates a row address of a memory cell array 35a, the row decoder 36b designates a row address of a memory cell array 35b, and the column decoder 40 designates each column address of the memory cell arrays 35a and 35b. A RAS signal, an R/W signal and a TE signal are applied to the timing generator 32. The timing generator 32 applies a switching signal to sense amplifiers 37a and 37b for controlling switching of data writing to the memory cell array 35a or 35b, or of reading the written data from the array 35a or 35b in response to a signal of a part of the row address signal.
A line test controller 33 applies a test pattern signal to registers 39a and 39b for controlling a line test. Coincidence detection circuits 38a and 38b determine whether test patterns stored in the registers 39a and 39b, and data stored in each column of each memory cell in the memory cell arrays 35a and 35b are coincident or not, and when not coincident, it outputs an error flag through an I/O buffer 34.
FIG. 14 is a diagram showing a part of an array structure of a conventional dynamic RAM self-containing a line mode test circuit. The example shown in FIG. 14 is described in "ISSCC89 Digest of Technical Papers FAM16.4" by the present inventors. Referring to FIG. 14, paired bit lines 1 and 2 are connected to a sense amplifier 5 and memory cells 22 are connected at intersections of the bit line 1 and a word line 13. In addition, the sense amplifier 5 is connected to a coincidence detection circuit 8 comprising, for example, an EXOR circuit and to one end of nodes 3 and 4 through transfer transistors 6 and 7.
The coincidence detection circuit 8 and a register 10 are connected to the nodes 3 and 4. The register 10 comprises two inverters having inputs and outputs connected to each other provided for latching input. The coincidence direction circuit 8 is provided for detecting whether the expectation latched in the register 10 and the data stored in a memory cell 22 are coincident or not. A pair of main I/O lines 11 and 12 are connected to the other ends of the nodes 3 and 4 through transfer transistors 20 and 21. A coincidence line 9 for outputting a line test result is connected to the coincidence detection circuit 8. The transfer transistors 6 and 7 are controlled by a clock signal .phi..sub.3 and the transfer transistors 20 and 21 are controlled by a column decoder output signal Yn.
FIG. 15 is a flow chart explaining an operation for performing a line test mode in a conventional dynamic RAM shown in FIG. 14, FIG. 16 is a diagram showing a memory cell array comprising a matrix of m rows x n columns, and FIG. 17 is a diagram showing one example of a test pattern for testing a line mode in a conventional dynamic RAM.
Now referring to FIGS. 13 to 17, a description will be given of an operation for testing a line mode in a conventional dynamic RAM. First, the column decoder output signal Yn is applied to the transfer transistors 20 and 21, so that the transfer transistors 20 and 21 are rendered conductive, thereby connecting the nodes 3 and 4 to the pair of main I/O lines 11 and 12. Then, a random test pattern column is inputted to be written in the register 10 through the pair of main I/O lines 11 and 12, the transfer transistors 20 and 21, and the nodes 3 and 4.
Then, the transfer transistors 6 and 7 are rendered conductive by the clock signal .phi..sub.3 and the word line 13 is driven, whereby the data written in the register 10 is transferred to the bit line pairs, 1 and 2, through the transfer transistors 6 and 7 to be inputted to a column in the memory cell 22 designated by the selected word line 13. When the memory array is structured by a matrix of m rows x n columns as shown in FIG. 16, n bit data is transferred, at one time, to a column of the memory cell. By performing such transfer operation m times, that is, to all the word lines, data is written in the whole memory array.
Reading operation will be performed in the following. More specifically, data in a column of the memory cell 22 selected by the single word line 13 has a small potential difference, so that it is amplified by the sense amplifier 5 to be read out onto the bit line pair, 1 and 2. On the other hand, the column of the expectation data is kept in a column of the register 10. At this time, the transfer transistors 6 and 7 are closed. The coincidence detection circuit 8 detects whether the data read out from the memory cell 22 onto the bit line pair of 1 and 2, and the expectation latched in the register 10 are coincident with each other or not. The detected result of coincidence is outputted to the coincidence line 9. More specifically, the coincidence line 9 is precharged to a high level and an output of the coincidence detection circuit 9 is wired OR connected, so that when any of data in columns in the memory cell 22 and data in columns of the register 10 is incoincident, a level of the coincidence line 9 is discharged to a lower level and a flag indicating the coincidence is outputted. By performing the reading operation for detecting coincidence (Line-Read Operation) m times to all the word lines, reading comparison of the whole memory array is completed.
Representing a single operation cycle time as t.sub.c, a test time necessary for performing a test will be represented as follows, EQU t=n.multidot.t.sub.c +m.multidot.t.sub.c +m.multidot.t.sub.c =t.sub.c (2m+n)
which is a total amount of register write time, copy write time and line read time. On the other hand, in a test, various test patterns are achieved in a large capacity DRAM in order to improve a detection sensitivity of interference between adjacent memory cells, and the like. Accordingly, a testing method is required in which a test pattern as random as possible can be implemented.
As described above, in a conventional dynamic RAM self-containing a line mode test circuit, although a test pattern can be random in a direction of the word line 13, a pattern in a direction of a bit line can only be the same. More specifically, as shown in FIG. 17, even though a random pattern can be produced in a column direction, only the same pattern can be produced in a row direction.